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ADP1763ACPZ0.95-R7 数据表(PDF) 18 Page - Analog Devices

部件名 ADP1763ACPZ0.95-R7
功能描述  CMOS Linear Regulator
PDF  19 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1763ACPZ0.95-R7 数据表(HTML) 18 Page - Analog Devices

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Data Sheet
ADP1763
Rev. 0 | Page 17 of 18
VIN – VOUT (V)
0
20
40
60
80
100
120
140
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
3A
2A
1A
500mA
10mA
100mA
TJ MAX
Figure 44. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP
TB = 92°C
TADP1763 =112°C
Figure 45. Thermal Image of the ADP1763 Evaluation Board at ILOAD = 3 A,
VIN = 1.5 V, VOUT = 1.3 V, TB = 92°C
Figure 45 shows a thermal image of the ADP1763 evaluation
board operating at a 3 A current load. The total power dissipation
on the ADP1763 is 600 mW, which makes the temperature on
the surface of the device higher by 30°C than the temperature of
the evaluation board.
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of ADP1763. However,
as shown in Table 8, a point of diminishing returns is eventually
reached, beyond which an increase in the copper size does not
yield significant heat dissipation benefits.
Use the following recommendations when designing PCBs:
Place the input capacitor as close as possible to the VIN
and GND pins.
Place the output capacitor as close as possible to the VOUT
and GND pins.
Place the soft start capacitor (CSS) as close as possible to the
SS pin.
Place the reference capacitor (CREF) and regulator capacitor
(CREG) as close as possible to the REFCAP pin and VREG pin,
respectively.
Connect the load as close as possible to the VOUT and
SENSE pins.
Use of 0603 or 0805 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.
Figure 46. Evaluation Board
Figure 47. Typical Board Layout, Top Side
Figure 48. Typical Board Layout, Bottom Side



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