ADP7157

Data Sheet

Rev. A | Page 14 of 23

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

The ADP7157 is supported by the ADIsimPower™ design tool set.

ADIsimPower is a collection of tools that produces complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance within minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and device count,

taking into consideration the operating conditions and limitations

of the IC and all real external components. For more information

about, and to obtain ADIsimPower design tools, visit

www.analog.com/ADIsimPower.

CAPACITOR SELECTION

Multilayer ceramic capacitors (MLCCs) combine small size, low

ESR, low effective series inductance (ESL), and wide operating

temperature range, making them an ideal choice for bypass

capacitors. They are not without faults, however. Depending on

the dielectric material, the capacit-ance can vary dramatically

with temperature, dc bias, and ac signal level. Therefore, selecting

the proper capacitor results in the best circuit performance.

Output Capacitor

The ADP7157 is designed for operation with ceramic capacitors

but functions with most commonly used capacitors when care

is taken with regard to the ESR value. The ESR of the output

capacitor affects the stability of the LDO control loop. A minimum

of 10 µF capacitance with an ESR of 0.2 Ω or less is recommended

to ensure the stability of the ADP7157. Output capacitance also

affects transient response to changes in load current. Using a

larger value of output capacitance improves the transient

response of the ADP7157 to large changes in load current.

Figure 44 shows the transient responses for an output

capacitance value of 10 µF.

CH2 5.00mV

M4.00µs

A CH1

700mA

B

W

B

W

SLEW RATE = 2.5A/µs

Input and VREG Capacitor

Connecting a 10 µF or greater capacitor from VIN to ground

reduces the circuit sensitivity to PCB layout, especially when

long input traces or high source impedance are encountered.

To maintain the best possible stability and PSRR performance,

connect a 1 µF or greater capacitor from VREG to ground.

REF Capacitor

amplifier. Connect a 1 µF or greater capacitor between REF and

ground

BYP Capacitor

buffer. A 1 µF capacitor is typically connected between BYP and

ground. Capacitors as small as 0.1 µF can be used; however, the

output noise voltage of the LDO increases as a result.

In addition, the BYP capacitor value can be increased to reduce

the noise below 1 kHz at the expense of increasing the start-up

the noise below 10 Hz. Tantalum capacitors are recommended

for capacitors larger than approximately 33 µF because solid

tantalum capacitors are less prone to microphonic noise issues.

A 1 μF ceramic capacitor in parallel with the larger tantalum

capacitor is recommended to ensure good noise performance at

higher frequencies.

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

1

10

100

1000

10Hz TO 100kHz

100Hz TO 100kHz