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ML610Q304 数据表(PDF) 2 Page - LAPIS Semiconductor Co., Ltd. |
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ML610Q304 数据表(HTML) 2 Page - LAPIS Semiconductor Co., Ltd. |
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2 / 28 page ![]() FEDL610Q304-01 ML610Q304 2/28 •Successive approximation type A/D converter − 10-bit A/D converter − Input: 3ch (ch0-2:External input) − Conversion time: 24.4 µs per channel at 4.096MHz VDD≧2.2V − Conversion time: 12.2 µs per channel at 8.192MHz VDD≧2.5V •Synchronous serial port − 2ch − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable •UART − Half-duplex × 1ch − TXD/RXD − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator •I2C bus interface − Slave function and Master function − Fast mode (400 kbps), standard mode (100 kbps) •General-purpose ports − Input-only port × 1ch − Output-only port × 3ch (including secondary functions) − Input/output × 11ch (including secondary functions)(P40 to P42 uses also as an A/D converter input port.) •Speaker amplifier(D-class) output power − 1.0W(at 5.0V)/0.45W(at 3.0V) − Disconnection detection circuit − Speaker pin short detection circuit − PLL oscillation stop detection reset •Reset − Reset through the RESET_N pin − Power-on reset generation when powered on − Reset by the watchdog timer (WDT) overflow − PLL oscillation stop detection reset •Clock − Low-speed clock Built-in RC oscillation (32.768 kHz) − High-speed clock Built-in PLL oscillation (4.096MHz,8.192MHz,etc) |
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