Data Sheet

ADP7157

Rev. A | Page 13 of 23

THEORY OF OPERATION

The ADP7157 is an ultralow noise, high PSRR linear regulator

targeting radio frequency (RF) applications. The input voltage

range is 2.3 V to 5.5 V, and the device delivers up to a 1.2 A load

current. The typical shut-down current consumption is 0.2 μA

at room temperature.

Optimized for use with 10 μF ceramic capacitors, the ADP7157

provides excellent transient performance.

VREG

GND

VOUT

VIN

EN

REF

REF_SENSE

REFERENCE

SHUTDOWN

CURRENT-LIMIT,

THERMAL

PROTECT

BYP

VOUT_SENSE

INTERNAL

REGULATOR

OTA

Figure 41. Simplified Internal Block Diagram

Internally, the ADP7157 consists of a reference, an error amplifier,

and a P-channel MOSFET pass transistor. The output current is

delivered via the PMOS pass device, which is controlled by the

error amplifier. The error amplifier compares the reference voltage

with the feedback voltage from the output and amplifies the

difference. If the feedback voltage is lower than the reference

voltage, the gate of the PMOS device pulls lower, allowing more

current to pass and increasing the output voltage. If the feedback

voltage is higher than the reference voltage, the gate of the

PMOS device pulls higher, allowing less current to pass and

decreasing the output voltage.

By heavily filtering the reference voltage, the ADP7157 achieves

1.7 nV/√Hz output typical from 10 kHz to 1 MHz. Because the

error amplifier is always in unity gain, the output noise is

independent of the output voltage.

The ADP7157 output voltage can be adjusted between 1.2 V and

3.3 V and is available in four models that optimize the input voltage

and output voltage ranges to keep power dissipation as low as

possible without compromising PSRR performance. The output

voltage is determined by an external voltage divider according

to the following equation:

VOUT = 1.2 V × (1 + R1/R2)

EN

BYP

VREG

ADP7157

REF_SENSE

VIN

VOUT

VOUT_SENSE

10µF

REF

GND

10µF

1µF

1µF

1µF

R1

1kΩ < R2 < 200kΩ

R2

ON

OFF

Figure 42. Typical Adjustable Output Voltage Application Schematic

The R2 value must be greater than 1 kΩ to prevent excessive

loading of the reference voltage appearing on the REF pin. To

minimize errors in the output voltage caused by the REF_

SENSE pin input current, the R2 value must be less than 200 kΩ.

For example, when R1 and R2 each equal 100 kΩ, the output

voltage is 2.4 V. The output voltage error introduced by the

REF_SENSE pin input current is 10 mV or 0.33%, assuming a

The ADP7157 uses the EN pin to enable and disable the VOUT pin

under normal operating conditions. When EN is high, VOUT

turns on, and when EN is low, VOUT turns off. For automatic

startup, tie EN to VIN.

VREG

VIN

REF

VOUT

VOUT_SENSE

REF_SENSE

BYP

GND

EN

7V

7V

4V

4V

4V

4V

4V

4V

4V

4V

7V

4V

4V

Figure 43. Simplified ESD Protection Block Diagram

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 43).