Data Sheet

ADP7156

Rev. A | Page 15 of 22

0.1

1

10

100

1k

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP7156 if they meet the minimum capacitance and maximum

ESR requirements. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior over tempera-

ture and applied voltage. Capacitors must have a dielectric adequate

to ensure the minimum capacitance over the necessary tempera-

ture range and dc bias conditions. X5R or X7R dielectrics with

a voltage rating of 6.3 V to 50 V are recommended. However,

Y5V and Z5U dielectrics are not recommended because of their

poor temperature and dc bias characteristics.

Figure 46 depicts the capacitance vs. dc bias voltage of a 1206,

10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is

strongly influenced by the capacitor size and voltage rating. In

general, a capacitor in a larger package or higher voltage rating

exhibits better stability. The temperature variation of the X5R

dielectric is ~±15% over the −40°C to +85°C temperature range

and is not a function of package or voltage rating.

DC BIAS VOLTAGE (V)

10

0

4

8

2

6

0

12

10

8

6

4

2

Figure 46. Capacitance vs. DC Bias Voltage

Use Equation 1 to determine the worst case capacitance

accounting for capacitor variation over temperature,

component tolerance, and voltage.

(1)

where:

tempco is the worst case capacitor temperature coefficient.

TOL is the worst case component tolerance.

In this example, the worst case temperature coefficient

(tempco) over −40°C to +85°C is assumed to be 15% for an X5R

dielectric. The tolerance of the capacitor (TOL) is assumed to

Substituting these values in Equation 1 yields

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP7156, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

UNDERVOLTAGE LOCKOUT (UVLO)

The ADP7156 also incorporates an internal UVLO circuit to

disable the output voltage when the input voltage is less than the

minimum input voltage rating of the regulator. The upper and

lower thresholds are internally fixed with 200 mV (typical) of

hysteresis.

0

0.5

1.0

1.5

2.0

2.5

1.9

2.0

2.1

2.2

2.3

+125°C

+25°C

–40°C

Figure 47 shows the typical behavior of the UVLO function.

This hysteresis prevents on/off oscillations that can occur when

caused by noise on the input voltage as it passes through the

threshold points.