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ADPD103

Data Sheet

Rev. B | Page 20 of 52

I2C SERIAL INTERFACE

The ADPD103 supports an I2C serial interface via the SDA

(data) and SCL (clock) pins. All internal registers are accessed

through the I2C interface.

The ADPD103 conforms to the UM10204 I2

C-Bus Specification

and User Manual, Rev. 05—9 October 2012, available from NXP

Semiconductors. It supports a fast mode (400 kbps) data transfer.

Figure 2 shows the timing diagram for the I2C interface.

Slave Address

The default 7-bit I2C slave address for the device is 0x64,

followed by the R/W bit. For a write, the default I2C slave

address is 0xC8; for a read, the default I2C address is 0xC9. The

slave address is configurable by writing to Register 0x09, Bits[7:1].

When multiple ADPD103 devices are on the same bus lines, the

INT and PDSO pins can be used to select specific devices for

the address change. Register 0x0D can be used to select a key to

enable address changes in specific devices. Use the following

procedure to change the slave address when multiple ADPD103

devices are connected to the same I2C bus lines:

1. Using Register 0x4F, enable the input buffer of the PDSO pin,

the INT pin, or both, depending on the key being used.

2. For the device identified as requiring an address change,

set the INT and/or PDSO pins high or low to match the

key being used.

3. Write the SLAVE_ADDRESS_KEY using Register 0x0D,

Bits[15:0] to match the desired function. The allowed keys

are shown in Table 24.

4. Write the desired SLAVE_ADDRESS using Register 0x09,

Bits[7:1]. While writing to Register 0x09, Bits[7:1], write

0xAD to Register 0x09, Bit[15:8]. Register 0x09 must be

written to immediately after writing to Register 0x0D.

5. Repeat Step 1 to Step 4 for all the devices that need the

SLAVE_ADDRESS changed.

6. Set the INT and PDSO pins as desired for normal operation

using the new SLAVE_ADDRESS for each device.

I2C Write and Read Operations

Figure 19 illustrates theADPD103 I2C write and read operations.

Single word and multiword read operations are supported. For a

single register read, the host sends a no acknowledge after the

second data byte is read and a new register address is needed for

each access.

For multiword operations, each pair of data bytes is followed by

an acknowledge from the host until the last byte of the last word is

read. The host indicates the last read word by sending a no

acknowledge. When reading from the FIFO (Register 0x60), the

data is automatically advanced to the next word in the FIFO

and the space is freed. When reading from other registers, the

except at Register 0x5F or Register 0x7F, where the address does

not increment. This allows lower overhead reading of sequential

registers.

All register writes are single word only and require 16 bits (one

word) of data.

The software reset (Register 0x0F, Bit 0) is the only command

that does not return an acknowledge because the command is

instantaneous.

Table 15. Definition of I2C Terminology

Term

Description

SCL

Serial clock.

SDA

Serial address and data.

Master

The master is the device that initiates a transfer, generates clock signals, and terminates a transfer.

Slave

The slave is the device addressed by a master. The ADPD103 operates as a slave device.

Start (S)

A high to low transition on the SDA line while SCL is high; all transactions begin with a start condition.

Start (Sr)

Repeated start condition.

Stop (P)

A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions.

ACK

During the acknowledge or no acknowledge clock pulse, the SDA line is pulled low and remains low.

NACK

During the acknowledge or no acknowledge clock pulse, the SDA line remains high.

Slave Address

After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write).

Read (R)

A 1 indicates a request for data.

Write (W)

A 0 indicates a transmission.

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