MCP1632-BAESLASHMS datasheet(13/34 Pages) MICROCHIP

13 / 34 page

 2013 Microchip Technology Inc.

DS20005254A-page 13

MCP1632

4.0

DETAILED DESCRIPTION

4.1

Device Overview

The MCP1632 device is comprised of an internal

oscillator, an internal constant current generator, a

high-speed comparator, a high-bandwidth amplifier, an

internal ramp generator for slope compensation and

logic gates, and is intended to be used to develop a

stand-alone switch-mode power supply. There are two

(orderable) switching frequency options for this device:

300 kHz or 600 kHz. Refer to Functional Block

Diagram for details about the internal functional blocks.

4.2

PWM Circuitry

MCP1632 implements a typical Peak Current Mode

control loop. The VEXT output of the MCP1632 device

is determined by the output level of the internal

high-speed comparator and the level of the internal

CLK signal. When the CLK signal level is high, the

PWM output (VEXT) is forced low, limiting the maximum

duty cycle to approximately 85% (typical). When the

CLK signal is low, the PWM output is determined by the

output level of the internal high-speed comparator.

During UVLO, the VEXT pin is held in low state. During

overtemperature

operation,

the

VEXT pin is

high-impedance (10 k

 to ground, typical).

4.3

Normal Cycle-by-Cycle Control

The beginning of a PWM cycle is defined by the internal

CLK signal (a transition from high to low). Refer to

Figure 4-1 for the detailed timing operation of the

MCP1632 PWM controller.

For normal operation, the state of the high-speed

comparator output (R) is low and the Q output of the

latch is low. On the high-to-low transition of the CLK

signal, the SR inputs to the high-speed latch are both

low and the Q output will remain unchanged (low). The

output of the OR gate (VDRIVE) will transition from high

to low, turning on the P-Channel drive transistor in the

output stage of the PWM. This will change the PWM

output (VEXT) from low to high, turning on the power

train MOSFET and ramping current in the power train

magnetic device. The sensed current in the magnetic

device is fed into the CS input, shown as a ramp, and

increases linearly until it reaches the same level as the

divided down output of the error amplifier at the

non-inverting input of the high-speed comparator. The

comparator output (R) changes state (low to high) and

resets the PWM latch. The Q output transition from low

to high turns off the VEXT drive to the external MOSFET

driver, thus terminating the current conduction cycle.

The CLK signal will transition from low to high while the

VEXT pin remains unchanged. If the CS input pin never

reaches the same level as the error amplifier output,

the low-to-high transition on the CLK signal terminates

the current switching cycle. This would be considered

as the maximum duty cycle. In either case, while the

CLK signal is high, the VEXT drive pin is low, turning off

the external power train switch. The next switching

cycle will start on another transition of the CLK signal

from high to low.

4.4

Error Amplifier/Comparator

Current Limit Function

The internal amplifier is used to create an error output

signal that is determined by the VREF input pin and the

power supply output voltage fed back into the FB pin.

The error amplifier output is rail-to-rail and is clamped

by a precision 2.7V internal voltage source. The output

of the error amplifier is then divided down 3:1 and

connected to the inverting input of the high-speed

comparator. The maximum output of the error amplifier

is 2.7V, so the maximum input to the inverting pin of the

high-speed comparator is 0.9V. As the output load

current demand increases, the error amplifier output

increases too, causing the inverting input pin of the

high-speed comparator to increase. Eventually, the

output of the error amplifier will hit the 2.7V clamp,

limiting the input of the high-speed comparator to 0.9V

maximum. Even if the FB input continues to decrease,

calling for more current, the inverting input is limited to

0.9V. By limiting the inverting input to 0.9V, the current

sense (CS) input is limited to 0.9V, thus limiting the

current that flows in the main switch. Limiting the

maximum peak current in the switch prevents the

destruction of the semiconductor device and the

saturation of the inductor during overloads. The resistor

divider placed at the output of the error amplifier

decreases the gain of the control loop by 9.5 dB. The

designer must take into account this gain reduction

during the compensation loop process. The error

amplifier

rail-to-rail

the

input

and

the

common-mode range includes the GND and VIN

potentials.

4.5

0% Duty Cycle Operation

The duty cycle of the VEXT output is capable of

reaching 0% when the FB pin (inverting error amplifier)

is held higher than the voltage present on the VREF

(Reference Voltage) pin. This is accomplished by the

rail-to-rail output capability of the error amplifier and the

offset voltage of the high-speed comparator. The

minimum error amplifier output voltage, divided by 3, is

less than the offset voltage of the high-speed

comparator. In case the output voltage of the converter

is above the desired regulation point, the FB input will

be above the VREF input and the error amplifier will be

pulled to the bottom rail (GND). This low voltage is

divided down 3:1 by the 2R and 1R resistor, and is

connected to the input of the high-speed comparator.

This voltage will be low enough so that there is no

triggering of the comparator, allowing narrow pulse

widths at VEXT.

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