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T2802-PLQ 数据表(PDF) 21 Page - ATMEL Corporation |
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T2802-PLQ 数据表(HTML) 21 Page - ATMEL Corporation |
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21 / 29 page ![]() 21 T2802 4509F–DECT–10/03 Output Power Settings Figure 4. 3-Wire Bus Protocol Timing Diagram Figure 5. TX DATA Timing With bits E11 - E12 PA (Output Power Settings) E12 E11 PA 0 0 -21 dBm 01 -11 dBm 10 -4 dBm 11 +3 dBm DATA CLOCK ENABLE TT TEC TS TC TH TL TPER Description Symbol Minimum Value Unit Clock period TPER 125 ns Set time data to clock TS 60 ns Hold time data to clock TH 60 ns Clock pulse width TC 125 ns Set time enable to clock TL 200 ns Hold time enable to data TEC 0 ns Time between two protocols TT 250 ns RefCLK TX_DATA T S T H Set-up time TX DATA TS > 8 ns When using REFCLK = 10.368 MHz, TS and TH must be considered for falling and rising edge of REFCLK Hold time TX DATA TH > 8 ns |
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