84326AM

www.icst.com/products/hiperclocks.html

REV. A MARCH 10, 2003

7

Integrated

Circuit

Systems, Inc.

ICS84326

PRELIMINARY

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS84326 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply plane

through vias, and bypass capacitors should be used for each

pin. To achieve optimum jitter performance, power supply iso-

lation is required.

Figure 1 illustrates how a 20

Ω resistor along

with a 10

µF and a .01µF bypass capacitor should be con-

nected to each V

20

Ω

V

CCA

10

µF

.01

µF

3.3V

.01

µF

V

CC

The clock layout topology shown below is a typical termina-

tion for 3.3V LVPECL outputs. The two different layouts

mentioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, termi-

nating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

3.3V

F

OUT

F

IN

5

Z

o

5

2

Z

o

3

2

Z

o

3

2

Z

Z

RTT =

1

(V

Z

o

Z

Z

50

Ω

50

Ω

RTT

V

F

IN

F

OUT

designed to drive 50

Ω transmission lines. Matched impedance

techniques should be used to maximize operating

frequency and minimize signal distortion.

Figures 2A and 2B

show two different layouts which are recommended only

as guidelines. Other suitable clock layouts may exist and it

would be recommended that the board designers simulate to

guarantee compatibility across all printed circuit and clock

component process variations.