MM5450/51

DS20005651A-page 8

 2016 Microchip Technology Inc.

3.0

FUNCTIONAL DESCRIPTION

The MM5450 and MM5451 are designed to drive either

4- or 5-digit alphanumeric LED displays with the added

benefit of requiring minimal interface with the display or

data source.

Data is transferred serially via two signals: clock and

serial data. Data transfer without the added

inconvenience

of

an

external

load

signal

is

accomplished by using a format of a leading “1”

followed by the allowed 35 data bits. These 35 data bits

are latched after the 36th has been transferred. This

scheme provides non-multiplexed, direct drive to the

LED display. Characters currently displayed (thus, data

output) changes only if the serial data bits differ from

those previously transferred.

Control of the output current for LED displays provides

for the display brightness. To prevent oscillations, a

1 nF capacitor should be connected to pin 19,

brightness control.

The Block Diagram is shown on page 1. For the

MIC5450, the /DATA ENABLE is a metal option and is

used instead of the 35th output. The output current is

typically 20-times greater than the current into pin 19,

which is set by an external variable resistor.

There is an external reset connection shown which is

available on unpackaged (die) only. Connection

Diagram: Die illustrates the die pad locations for

bonding in “chip on board” applications.

Figure 3-1 shows the input data format. A leading “1” is

followed by 35 bits of data. After the 36th had been

transferred, a LOAD signal is generated synchronously

with the clock high state. This loads the 35 bits of data

into the latches. The low side of the clock is used to

generate a RESET signal which clears all shift registers

for the next set of data. All shift registers are static

master-slave, with no clear for the master portion of the

first register, allowing continuous operation.

FIGURE 3-1:

Input Data Format.

There must be a complete set of 36 clocks or the shift

registers will not clear.

When the chip first powers ON, an internal power ON

reset signal is generated that resets all registers and all

latches. The START bit and the first clock return the

chip to its normal operation.

The Connection Diagram: Dual-Inline Package (DIP)

and Connection Diagram: Plastic-Leaded Chip Carrier

(PLCC) show the pinout of the MIC5450 and MIC5451.

Bit 1 is the first bit following the start bit and it will

appear on pin 18. A logical “1” at the input will turn on

the appropriate LED.

Figure 3-2 shows the timing relationships between

data, clock and /DATA ENABLE. A maximum clock

frequency of 0.5 MHz is assumed.

FIGURE 3-2:

Timing Diagram.

For applications where a lesser number of outputs is

used, it is possible to either increase the current per

following equation can be used for calculations.

EQUATION 3-1:

Equation 3-1 is used to plot Figure 2-1, Figure 2-2, and

Figure 2-3.

CLOCK

1

DATA

LOAD

(INTERNAL)

RESET

(INTERNAL)

START BIT 1

BIT 36

36

37

BIT 35

CLOCK

DATA

DATA ENABLE

300 nS MIN

100 nS MIN

T

J

V

OUT

I

LED



No of segments



124

o

C/W

T

A

+



=

Where:

Junction Temperature (+150°C max.)

Voltage at the LED driver outputs

LED current

124°C/W Thermal resistance of the package

Ambient temperature