Field Programmable Dual Output SS VersaClock

MDS 342 F

5

Revision 090704

Integrated Circuit Systems, Inc.

ICS342

Note 1: Example with 25 MHz crystal input with two outputs of 33.3 MHz, no load, and VDD = 3.3 V.

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85

° C

Note 1: Measured with 15 pF load.

Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.

Note 3: ICS test mode output occurs for first 170 clock cycles on CLK2 for each PLL powered up. PDTS

transition high on select address change.

Output High Voltage

(CMOS High)

VDD-0.4

V

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Short Circuit Current

±70

mA

Nominal Output

Impedance

20

Ω

Internal pull-up resistor

SEL, PDTS pins

250

k

Ω

Internal pull-down

resistor

CLK output

525

k

Ω

Input Capacitance

Inputs

4

pF

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

Fundamental Crystal

5

27

MHz

Input Clock

2

50

MHz

Output Frequency

0.25

200

MHz

Output Rise Time

20% to 80%, Note 1

1

ns

Output Fall Time

80% to 20%, Note 1

1

ns

Duty Cycle

Note 2

40

49-51

60

%

Power-up time

PLL lock time from

power-up, Note 3

410

ms

PDTS goes high until

stable CLK output, Spread

Spectrum Off, Note 3

0.2

2

ms

PDTS goes high until

stable CLK output, Spread

Spectrum On, Note 3

47

ms

One Sigma Clock Period Jitter

Configuration Dependent

50

ps

Maximum Absolute Jitter

Deviation from Mean.

Configuration Dependent

+200

ps

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units