CL-PD6722 datasheet(13/128 Pages) CIRRUS

13 / 128 page

CL-PD6710/’22

ISA–to–PC-Card Host Adapters

May 1997

PRELIMINARY DATA SHEET v3.1

PIN INFORMATION

PWRGOOD

Power Good: The CL-PD67XX will be reset

when the POWERGOOD input is low. Connect

to the POWERGOOD signal from the system

power supply; or, if not available, connect to

inverted RESETDRV signal from ISA bus.

141

201

–

AEN

Address Enable: This is an input from the

host CPU bus signal that distinguishes

between DMA and non-DMA bus cycles. This

input should be high for a DMA cycle and will

cause the CL-PD67XX to ignore IOR* and

IOW* except when a CL-PD6722 is conﬁgured

for DMA and its DREQ (IRQ10) and DACK*

(IRQ9) signals are active. Connect to ISA sig-

nal AEN.

When CL-PD67XX is in Suspend mode (see

Misc Control 2, bit 2 on page 61), pull this input

high during system power-down for lowest

power consumption.

126

187

–

MEMCS16*

Memory Select 16: This output is an acknowl-

edge of 16-bit-wide access support and is gen-

erated by the CL-PD67XX when a valid 16-bit-

word-accessible memory address has been

decoded. Connect to ISA signal MEMCS16*.

160

O-

IOCS16*

I/O Select 16: This output is an acknowledge

for 16-bit-wide access support and is gener-

ated by the CL-PD67XX when a valid 16-bit

word accessible I/O address has been

decoded. Connect to ISA signal IOCS16*.

158

O-

IOCHRDY

I/O Channel Ready: This output is driven low

by the CL-PD67XX to lengthen host cycles.

Connect to the ISA bus IOCHRDY signal.

127

188

O-

IRQ[14, 11,

7, 5:3]

Interrupt Request: These outputs indicate

programmable interrupt requests generated

from any of a number of card actions. Although

there is no speciﬁc mapping requirement for

connecting interrupt lines from the

CL-PD67XX to the system, a common use is

to connect these pins to the corresponding ISA

signal names in the system.

86, 93, 116,

113, 111, 109

148, 154, 177,

174, 172, 170

O-

2 mA

IRQ9

Interrupt Request 9: In default mode this out-

put indicates an interrupt request from one of

the cards.

When the CL-PD6722 is in DMA mode (see

Misc Control 2, bit 6), IRQ9 becomes an input

and is connected to the ISA bus DACK* line

corresponding to the ISA bus DREQ line that

the IRQ10 pin is connected to. In DMA mode

this signal is active-low.

138

198

I/O-

2 mA

Table 2-1.

ISA Bus Interface Pins (cont.)

Pin Name

Description

Pin Number

Qty.

I/O

Pwr. Drive

CL-PD6710

CL-PD6722

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