Supertex inc.

Supertex inc.

www.supertex.com

Doc.# DSFP-TP2522

C081413

TP2522

= “Green” Packaging

Features

Applications

General Description

This low threshold enhancement-mode (normally-off)

transistor utilizes a vertical DMOS structure and Supertex’s

well-proven silicon-gate manufacturing process. This

combination produces a device with the power handling

capabilities of bipolar transistors and with the high input

impedance and positive temperature coefficient inherent

in MOS devices. Characteristic of all MOS structures, this

device is free from thermal runaway and thermally-induced

secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very

low threshold voltage, high breakdown voltage, high input

impedance, low input capacitance, and fast switching speeds

are desired.

Pin Configuration

Product Marking

TO-243AA (SOT-89)

TO-243AA (SOT-89)

GATE

SOURCE

DRAIN

DRAIN

P-Channel Enhancement-Mode

Vertical DMOS FET

Absolute Maximum Ratings

Parameter

Value

Drain-to-source voltage

BV

DSS

Drain-to-gate voltage

BV

DGS

Gate-to-source voltage

±20V

Operating and storage temperature

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

Ordering Information

Part Number

Package Option

Packing

TP2522N8-G

TO-243AA (SOT-89)

2000/Reel

Product Summary

BV

R

DS(ON)

(max)

V

GS(th)

(max)

I

D(ON)

(min)

-220V

12Ω

-2.4V

-750mA

-G denotes a lead (Pb)-free / RoHS compliant package.

Contact factory for Wafer / Die availablity.

Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.

Typical Thermal Resistance

Package

θ

ja

TO-243AA (SOT-89)

Package may or may not include the following marks: Si or