Supertex inc.

Supertex inc.

www.supertex.com

Doc.# DSFP-TN2524

C080913

TN2524

= “Green” Packaging

Features

Applications

General Description

This low threshold, enhancement-mode (normally-off)

transistor utilizes a vertical DMOS structure and Supertex’s

well-proven, silicon-gate manufacturing process. This

combination produces a device with the power handling

capabilities of bipolar transistors and with the high input

impedance and positive temperature coefficient inherent

in MOS devices. Characteristic of all MOS structures, this

device is free from thermal runaway and thermally-induced

secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

very low threshold voltage, high breakdown voltage, high

input impedance, low input capacitance, and fast switching

speeds are desired.

N-Channel Enhancement-Mode

Vertical DMOS FET

Absolute Maximum Ratings

Parameter

Value

Drain-to-source voltage

BV

DSS

Drain-to-gate voltage

BV

DGS

Gate-to-source voltage

±20V

Operating and storage temperature

Absolute Maximum Ratings are those values beyond which damage to the device may

occur. Functional operation under these conditions is not implied. Continuous operation

of the device at the absolute rating level may affect device reliability. All voltages are

referenced to device ground.

Product Marking

TO-243AA (SOT-89)

Package may or may not include the following marks: Si or

Pin Configuration

TO-243AA (SOT-89)

GATE

SOURCE

DRAIN

DRAIN

Product Summary

BV

R

DS(ON)

(max)

I

D(ON)

(min)

V

GS(TH)

(max)

240V

6.0Ω

1.0A

2.0V

Typical Thermal Resistance

Package

θ

ja

TO-243AA (SOT-89)

Ordering Information

Part Number

Package Option

Packing

TN2524N8-G

TO-243AA (SOT-89)

2000/Reel

-G denotes a lead (Pb)-free / RoHS compliant package.

Contact factory for Wafer / Die availablity.

Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.