V370PDC

Copyright © 1999, V3 Semiconductor Corp.

V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101

13

Notes:

1. Applies only to READY pin when i960_RDY bit in LB_BUS_CFG register is set to ’1’.

Table 12: Local Bus Timing Parameters for Vcc =3.3 Volts +/- 5%

66MHz

#

Symbol

Description

Notes

Min

Max

Units

CLKIN period

15

ns

CLKIN high time

5.5

ns

CLKIN low time

5.5

ns

Synchronous input setup

3

ns

4a

Asynchronous input setup (READY)1

7

ns

Synchronous input hold

1

ns

CLKIN to output valid delay

3

11

ns

CLKIN to output driving delay

3

11

ns

CLKIN to high impedance delay

4

12

ns

ALE Pulse Width

ns

10

CLKIN rising to ALE rising

2

10

ns

11

CLKIN falling to ALE falling

2

10

ns

Table 13: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10%

#

Symbol

Description

Notes

Min

Max

Units

PCLK period

30

ns

Synchronous input setup to PCLK

1

7

ns

Synchronous input hold from PCLK

0

ns

PCLK to output valid delay

2

3

11

ns

PCLK to output driving delay

4

11

ns

PCLK to high impedance delay

5

18

ns

Reset period when PRST used as input