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PSOC4100M 数据表(PDF) 13 Page - Cypress Semiconductor

部件名 PSOC4100M
功能描述  Programmable System-on-Chip
PDF  41 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

PSOC4100M 数据表(HTML) 13 Page - Cypress Semiconductor

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PSoC® 4: PSoC 4100M Family
Datasheet
Document Number: 001-96519 Rev. *E
Page 13 of 41
Power
The supply voltage range is 1.71 to 5.5 V with all functions and
circuits operating over that range.
The PSoC 4100M family allows two distinct modes of power
supply operation: Unregulated External Supply and Regulated
External Supply modes.
Unregulated External Supply
In this mode, the PSoC 4100M is powered by an External Power
Supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation, for
instance, the chip can be powered from a battery system that
starts at 3.5V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4100M supplies the internal logic and the
VCCD output of the PSoC 4100M must be bypassed to ground
via an external Capacitor (in the range of 1 to 1.6 µF; X5R
ceramic or better).
The grounds, VSSA and VSS, must be shorted together. Bypass
capacitors must be used from VDDD and VDDA to ground,
typical practice for systems in this frequency range is to use a
capacitor in the 1 µF range in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead
inductance, and the Bypass capacitor parasitic should be
simulated to design and obtain optimal bypassing.
Regulated External Supply
In this mode, the PSoC 4100M is powered by an external power
supply that must be within the range of 1.71 to 1.89 V (1.8 ±5%);
note that this range needs to include power supply ripple. VCCD
and VDDD pins are shorted together and bypassed. The internal
regulator is disabled in firmware.
Power Supply
Bypass Capacitors
VDDD–VSS and
VDDIO-VSS
0.1 µF ceramic at each pin plus bulk
capacitor 1 to 10 µF.
VDDA–VSSA
0.1 µF ceramic at pin. Additional 1 µF to
10 µF bulk capacitor
VCCD–VSS
1 µF ceramic capacitor at the VCCD pin
VREF–VSSA
(optional)
The internal bandgap may be bypassed
with a 1 µF to 10 µF capacitor for better
ADC performance.



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