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NLAS4053 数据表(PDF) 3 Page - ON Semiconductor |
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NLAS4053 数据表(HTML) 3 Page - ON Semiconductor |
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3 / 14 page ![]() NLAS4053 http://onsemi.com 3 MAXIMUM RATINGS Symbol Parameter Value Unit VEE Negative DC Supply Voltage (Referenced to GND) −7.0 to )0.5 V VCC Positive DC Supply Voltage (Note 1) (Referenced to GND) (Referenced to VEE) −0.5 to )7.0 −0.5 to )7.0 V VIS Analog Input Voltage VEE −0.5 to VCC )0.5 V VIN Digital Input Voltage (Referenced to GND) −0.5 to 7.0 V I DC Current, Into or Out of Any Pin $50 mA TSTG Storage Temperature Range −65 to )150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction Temperature under Bias )150 _C qJA Thermal Resistance SOIC TSSOP 143 164 °C/W PD Power Dissipation in Still Air, SOIC TSSOP 500 450 mW MSL Moisture Sensitivity Level 1 FR Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in VESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) u2000 u200 u1000 V ILATCHUP Latchup Performance Above VCC and Below GND at 125°C (Note 5) $300 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The absolute value of VCC $ |VEE| ≤ 7.0. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VEE Negative DC Supply Voltage (Referenced to GND) −5.5 GND V VCC Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) 2.5 2.5 5.5 6.6 V VIS Analog Input Voltage VEE VCC V VIN Digital Input Voltage (Note 6) (Referenced to GND) 0 5.5 V TA Operating Temperature Range, All Package Types −55 125 _C tr, tf Input Rise/Fall Time VCC = 3.0 V $ 0.3 V (Channel Select or Enable Inputs) VCC = 5.0 V $ 0.5 V 0 0 100 20 ns/V 6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level. |
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