DM9102AT datasheet(39/77 Pages) ETC

39 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

CardBus Status Changed Registers

The DM9102A implements four status changed registers.

These status changed registers are accessed by the

CardBus systom software. These registers are mapped

only to the memory address space and not to the I/O

address space.

1. Function Event Register: (offset 80h)

Bit

Name

Default

Description

0:3

Reserved

R/W

Unpredictable on read

General Wake-up

Event

R/WC

This bit is set when the DM9102A has detected a power management event.

This bit is cleared upon power-up reset and by write 1. It is unaffected by either

hardware or software reset. When the PME_Status bit in the PCI configuration is

cleared, this bit is automatically cleared as well.

5:14

Reserved

R/W

Unpredictable on read

Interrupt

R/WC

This bit is set when there is an interrupt pending.

This bit is cleared by write 1. This bit is cleared upon hardware or software reset.

16:31

Reserved

R/W

Unpredictable on read

2. Function Event Mask Register: (offset 84h)

Bit

Name

Default

Description

0:3

Reserved

R/W

Unpredictable on read

General Wake-up

Event Enable

R/WC

When set together with the Wake-up Event Summary Enable bit (Function Event

Mask Register<14>), enables the assertion of the CSTSCHG pin.

To disable the assertion of the CSTSCHG, the PME_Enable bit in the PCI

configuration register (PMC<8>) must be cleared as well.

This bit is cleared upon power up reset.

5:13

Reserved

R/W

Unpredictable on read

Wake-up Event

Summary Enable

R/W

When set together with the General Wake-up Event Enable bit (Function Event

Mask Register<4>), enables the assertion of the CSTSCHG pin.

To disable the assertion of the CSTSCHG pin, the PME_Enable bit in the PCI

configuration register (PMC<8>) must be cleared as well.

This is cleared upon power up reset.

Interrupt Register

Enable

R/W

When set, enable the assertion of the interrupt pin (INT#).

This bit is cleared upon hardware or software reset.

16:31

Reserved

R/W

Unpredictable on read

3. Function Present State Register: (offset 88h)

Bit

Name

Default

Description

0:3

Reserved

R/W

Unpredictable on read

DM9102AT 数据表(PDF) 39 Page - List of Unclassifed Manufacturers

DM9102AT 数据表(HTML) 39 Page - List of Unclassifed Manufacturers

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DM9102AT 数据表(PDF) 39 Page - List of Unclassifed Manufacturers

DM9102AT 数据表(HTML) 39 Page - List of Unclassifed Manufacturers

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