MP7542

5

Rev. 2.00

Figure 1. Timing Diagram

ADDRESS BUS VALID

DATA

BUS VALID

A0 - A1

CS

WR

DB3 - DB0

MP7542 Operation

MP7542 Control Inputs

CS

WR

XXX

Resets DAC 12-bit register to code 0000 0000 0000

NOTES

1.

1 indicates logic HIGH

2.

0 indicates logic LOW

3.

X indicates don’t care

4.

indicates LOW to HIGH transition

5.

MSB

XXXX

XXXX

XXXX

LSB

6.

Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to

latch data and using CS as a device enable.

Table 1. Truth Table

CLR

X

0

0

0

0

1

1

1

1

X

0

0

1

1

0

0

1

1

1

0

0

0

0

0

X

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

No operation; device not selected

Load LOW byte data register on edges as shown

Load MIDDLE byte data register on edges as shown

Load HIGH byte data register on edges as shown

Load 12-bit DAC register with data in LOW byte, MIDDLE

byte, & HIGH byte data registers

Load applicable

data register

with data at

high

byte

middle

byte

low

byte