MP7528

9

Rev. 2.00

MICROPROCESSOR INTERFACE

DAC A

DAC B

Data Bus

DB0

DB7

Address

Decode

Logic

A0-A15

D0–D7

A+1**

A*

MP7528

CPU

6800

Analog circuitry has been omitted for clarity

*A = Decoded 7528 DAC A Address

**A + 1 = Decoded 7528 DAC B Address

Figure 2. MP7528 Dual DAC to 6800

CPU Interface

DAC A

DAC B

ADDR/Data Bus

DB0

DB7

A8-A15

AD0–AD7

Address

Decode

Logic

A+1**

A*

MP7528

CPU

8085

Figure 3. MP7528 Dual DAC to 8085

CPU Interface

Latch

8212

ALE

NOTE:

8085 instruction SHLD (store H & L direct) can update

both DACS with data from H and L registers

Analog circuitry has been omitted for clarity

*A = Decoded 7528 DAC A Address

**A + 1 = Decoded 7528 DAC B Address

Address Bus

Address Bus

DACA/DACB

CS

WR

WR

DACA/DACB

CS

WR

PERFORMANCE CHARACTERISTICS

Graph 1. Relative Accuracy vs. Digital Code

5 V

Graph 2. Relative Accuracy vs. Digital Code

15 V