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APPLICATION INFORMATION

TYPICAL CIRCUIT CONNECTION DIAGRAM

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PCM1803

AGND

PDWN

BYPAS

TEST

LRCK

MODE1

DGND

MODE0

FMT1

FMT0

OSR

DOUT

BCK

SCKI

+

Oversampling

System Clock

L-Ch IN

R-Ch IN

+5 V

+

Power Down

LCF Bypass

Control

+

L/R Clock

Audio Data

Processor

Mode [1:0]

Format [1:0]

+3.3 V

Data Clock

Data Out

+

+

Control

S0026-01

+

BOARD DESIGN and LAYOUT CONSIDERATIONS

AGND, DGND Pins

PCM1803

SLES125 – NOVEMBER 2004

Figure 23 illustrates a typical circuit connection diagram where the cutoff frequency of the input HPF is about

160 kHz.

NOTES:

A.

operation, and requires a power-on settling time with a 40-ms time constant during the power-on initialization period.

B.

C.

D.

frequency for the antialiasing filter in normal operation.

Figure 23. Typical Application Diagram

The digital and analog power-supply lines to the PCM1803 should be bypassed to the corresponding ground pins

with 0.1-

µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic

performance of the ADC.

To maximize the dynamic performance of the PCM1803, the analog and digital grounds are not connected

internally. These grounds should have low impedance to avoid digital noise feeding back into the analog ground.

Therefore, they should be connected directly to each other under the part to reduce potential noise problems.

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