IP1001 datasheet(13/18 Pages) IRF

13 / 18 page

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iP1001

For stable and noise free operation of the whole

power system it is recommended that the designer

uses to the following guidelines.

1. Follow the layout scheme presented in Fig.9.

Make sure that the output inductor L1 is placed as

close to the iP1001 as possible to prevent noise

propagation that can be caused by switching of

power at the switching node V

SW, to sensitive circuits.

2. Provide a mid-layer solid ground with connections

to the top layer through vias. The two PGND pads of

the iP1001 also need to be connected to the same

ground plane through vias.

3. Do not connect SGND pins of the iP1001 to PGND.

4. To increase power supply noise immunity, place

input and output capacitors close to one another, as

shown in the layout diagram. This will provide short

high current paths that are essential at the ground

terminals.

Fig 9. iP1001 suggested layout

5. Although there is a certain degree of V

bypassing inside the iP1001, the external input

decoupling capacitors should be as close to the

device as possible.

6. In situations where the load is located at an

appreciable distance from the iP1001 block, it is

recommended that at least one or two capacitors

be placed close to the iP1001 to derive the V

signal.

7. The V

F connection to the output capacitors should

be as short as possible and should be routed as

far away from noise generating traces as possible.

8. V

FS & GNDS pins need to be connected at the

load for remote sensing. If remote sensing is not

used connect V

FS to VF and GNDS to PGND.

9. Refer to IR application note AN-1029 to determine

what size vias and what copper weight and

thickness to use when designing the PCB.

Layout Guidelines

Input

Terminal

Load

Terminal

OUT

Output Caps (C

OUT)

Input Caps (C

IN)

PGND

Output Inductor (L

PGND

iP1001 Block

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