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AP2003SL 数据表(PDF) 5 Page - Anachip Corp |
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AP2003SL 数据表(HTML) 5 Page - Anachip Corp |
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5 / 6 page ![]() AP2003 Synchronous PWM Controller (Preliminary) Anachip Corp. www.anachip.com.tw Rev. 0.1 Feb.10, 2004 5/6 Function Description Synchronous Buck Converter Primary VCORE power is provided by a synchronous, voltage-mode pulse width modulated (PWM) controller. This section has all the features required to build a high efficiency synchronous buck converter, shutdown function. The output voltage of the synchronous converter is set and controlled by the output of the error amplifier. The external resistive divider reference voltage is derived from an internal trimmed band-gap voltage reference. The inverting input of the error amplifier receives its voltage from the SENSE pin. The internal oscillator uses an on-chip capacitor and trimmed precision current sources to set the oscillation frequency to 200KHz. The triangular output of the oscillator sets the reference voltage at the inverting input of the comparator. When the oscillator output voltage drops below the error amplifier output voltage, the comparator output goes high. This pulls DRVL low, turning off the low-side FET, and DRVH is pulled high, turning on the high-side FET (once the cross-current control allows it). When the oscillator voltage rises back above the error amplifier output voltage, the comparator output goes low. This pulls DRVH low, turning off the high-side FET, and DRVL is pulled high, turning on the low-side FET (once the cross-current control allows it). As SENSE increases, the output voltage of the error amplifier decreases. This causes a reduction in the on-time of the high-side MOSFET connected to DRVH, hence lowering the output voltage. Under Voltage Lockout The under voltage lockout circuit of the AP2003 assures that the high-side MOSFET driver outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if VCC falls below 4.1V. Normal operation resumes once VCC rises above 4.2V. Soft Start Initially, SS/ SHDN sources 10uA of current to charge an external capacitor. The outputs of the error amplifiers are clamped to a voltage proportional to the voltage on SS/ SHDN . This limits the on-time of the high-side MOSFETs, thus leading to a controlled ramp-up of the output voltages. Hiccup Mode During power up, the SS/ SHDN pin is internally pulled low until VCC reaches the under-voltage lockout level of 4.2V. Once VCC has reached 4.2V, the SS/ SHDN pin is released and begins to source 10uA of current to the external soft-start capacitor. As the soft-start voltage rises, the output of the internal error amplifier is clamped to this voltage. When the error signal reaches the level of the internal triangular oscillator, which swings from 1V to 2V at a fixed frequency of 200KHz, switching occurs. As the error signal crosses over the oscillator signal, the duty cycle of the PWM signal continues to increase until the output comes into regulation. The soft-start voltage will begin to decrease as the 2uA of current discharge the external capacitor. When the soft-start voltage reaches 0.8V, the SS/ SHDN pin will begin to source 10uA and begin to charge the external capacitor causing the soft-start voltage to rise again. Again, when the soft-start voltage reaches the level of the internal oscillator, switching will occur. In conclusion, above is shown a typical “12V Application Circuit” which has a BSTH voltage derived by bootstrapping input voltage to the PHASE node through diode D2. This circuit is very useful in cases where only single input power of 5V(or 12V) is available. In order to prevent substrate glitching, a small-signal diode should be placed in close proximity to the chip with cathode connected to PHASE and anode connected to GND. |
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