The maximum allowable power losses can be calculated

using the following equation:

JA

JMAX

A

DMAX

TT

P

−

=

θ

where:

mum allowed junction temperature.

PCB Layout Guidelines

Careful PCB layout is critical to achieving low switching

losses and clean, stable operation.

Use the following guidelines for good PCB layout:

● Keep the input capacitors as close as possible to the

IN and PGND pins.

● Keep the output capacitors as close as possible to

the OUT and PGND pins.

● Keep the resistive feedback dividers as close as

possible to the FB pin.

● Connect all of the PGND connections to as large as

copper plane area as possible on the top layer.

● Connect EP1 to PGND and GND planes on bottom

layer.

● Use multiple vias to connect internal PGND planes

to the top layer PGND plane.

● Do not keep any solder mask on EP1, EP2, and EP3

on bottom layer. Keeping solder mask on exposed

pads decreases the heat dissipating capability.

● Keep the power traces and load connections short.

This practice is essential for high efficiency.

Using thick copper PCBs (2oz vs. 1oz) can enhance

full-load efficiency. Correctly routing PCB traces is

a difficult task that must be approached in terms of

fractions of centimeters, where a single milliohm of

excess trace resistance causes a measurable

efficiency penalty.

Layout Recommendation

www.maximintegrated.com

Maxim Integrated │ 16

MAXM17543

4.5V to 42V, 2.5A High-Efficiency, DC-DC Step-Down

Power Module with Integrated Inductor

PGND

OUT

SGND

OUT

12

9

8

6

5

3

2

11

4

29 28

25

26

27

23

24

13 14 15

16

17

18

19

20

21

22

10

7

1

OUT

EP1

EP2

EP3

P

IN

GND

PGND