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831752 数据表(PDF) 11 Page - Integrated Device Technology |
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831752 数据表(HTML) 11 Page - Integrated Device Technology |
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11 / 18 page ![]() 11 ©2016 Integrated Device Technology, Inc Revision B June 28, 2016 831752 Data Sheet 2.5V Differential Clock Input Interface The CLK/nCLK accepts HCSL, LVDS and LVPECL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 4A to 4 E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The figures below also apply to FCLK/ nFCLK operating as an input. Figure 4A. CLK/nCLK Input Driven by a 2.5V LVPECL Driver Figure 4C. CLK/nCLK Input Driven by a 2.5V LVPECL Driver Figure 4E. CLK/nCLK Input Driven by a 2.5V LVDS Driver Figure 4B. CLK/nCLK Input Driven by a 2.5V HCSL Driver Figure 4D. CLK/nCLK Input Driven by a 2.5V LVPECL Driver with AC Couple HCSL *R3 33 *R4 33 CLK nCLK 2.5V 2.5V Zo = 50 Zo = 50 Differential Input R1 50 R2 50 *Optional – R3 and R4 can be 0 R1 125 R2 125 R5 100 - 200 R6 100 - 200 CLK nCLK 2.5V LVPECL 2.5V Zo = 50 Ω Zo = 50 Ω 2.5V Differential Input C1 C2 R3 84 R4 84 2.5V |
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