Silicon limitations

STM8AL3xxx STM8L052R8 STM8L1xxx6/8

16/18

DocID17922 Rev 6

PE flag can be cleared in USART Duplex mode by writing to the data register

Description

The PE flag can be cleared by a read to the USART_SR register followed by a read or a

write to the USART_DR register.

When working in duplex mode, the following event can occur: the PE flag set by the receiver

at the end of a reception is cleared by the software transmitter reading the USART_SR (to

check TXE or TC flags) and writing a new data into the USART_DR.

The software receiver can also read a PE flag at ‘0’ if a parity error occurred.

Workaround

The PE flag should be checked before writing to the USART_DR.

PE flag is not set in USART Mute mode using address mark detection

Description

If, when using address mark detection, the receiver recognizes in Mute mode a valid

address frame but the parity check fails, it exits from the Mute mode without setting the PE

flag.

Workaround

None.

IDLE flag is not set using address mark detection in the USART peripheral

Description

The IDLE flag is not set when the address mark detection is enabled, even when the

USART is in Run mode (not only in Mute mode).

Workaround

None.

1.3.4

Timer limitations

TIM1 advanced timer: Bad regulation for 100% PWM

Description

When the OCREFCLR functionality is activated, the OCxREF signal becomes deasserted

(and consequently OCx is deasserted / OCxN is asserted) when a high level is applied on

the OCREF_CLR signal. Then, the PWM restarts (output re-enabled) at the next counter

overflow.

But if the PWM is configured at 100% (CCxR->ARR), then it does not restart and OCxREF

remains de-asserted.

Consequently, current feedbacks cannot be generated without programming a minimum off-

time (there cannot be a 100% PWM for this usage).

Workaround

None.

No fix planned for this limitation.