STLUX385ATR datasheet(39/126 Pages) STMICROELECTRONICS

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STLUX

I/O multifunction signal configuration

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7.3.1

Port P1 I/O multiplexing signal

Figure 11 shows an outline view of the port P1 signal multiplexing scheme.

Figure 11. Port P1 I/O multiplexing scheme

Note:

The P1 [5:0] output signals may be read back from the P1_IDR register only when the pins

are configured as GPIO out or PWM signals.

The PWM internal signal is read back also by its own SMED through the

SMD<n>_FSM_STS register.

Verify pin availability in device pin Table 4 on page 32.

7.3.2

P1 programmable pull-up feature

The pad pull-up resistances (47 k

) of the Port1 may be configured through the GPIO1

internal register.

7.4

Port P2 I/O multifunction configuration signal

The Port2 I/O multifunction pins, similarly to the Port0 and Port2, can be individually

configured through the following set of registers based on the selected device configuration

policy:



Cold configuration: AFR_IOMXP2 option byte registers (refer to Section 10: Option

bytes on page 60. After reset the P2 signals are configured in line with AFR_IOMXP2

contents.



Warm configuration: MSC_IOMXP2 miscellaneous register (refer to Section 7.5). After

reset the P2 signals are configured as DIGIN input lines with the pull-up enabled.

Table 8 summarizes the port P2 configurations selected by the register fields

Sel_p25…Sel_p20 which respectively control the bits [5]… [0] of port P2. The P2 [0] is

configured by the CCOEN bit field of the register CKC_CCOR. The SWIM alternate function

signal (when available) is controlled by the Sel_SWIM bit field provided by registers

AFR_IOMXP2 [7] and MSC_IOMXP2 [7].

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