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STM8AL3L8x 数据表(PDF) 113 Page - STMicroelectronics |
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STM8AL3L8x 数据表(HTML) 113 Page - STMicroelectronics |
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113 / 131 page  DocID027179 Rev 6 113/131 STM8AL318x STM8AL3L8x Electrical parameters 117 Figure 42. ADC1 accuracy characteristics Figure 43. Typical connection diagram using the ADC 1. Refer to Table 56 for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 44 or Figure 45, depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF capacitors should be used. They should be placed as close as possible to the chip. Offset Offset error 2 3 LSB Gain Gain error 2 3 LSB 1. Guaranteed by characterization results. Table 59. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V (continued) Symbol Parameter Typ. Max.(1) Unit |
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