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STM32F303XD 数据表(PDF) 25 Page - STMicroelectronics |
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STM32F303XD 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 173 page  DocID026415 Rev 5 25/173 STM32F303xD STM32F303xE Functional overview 67 • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability (for each channel) • External triggers for conversion • Input voltage reference VREF+ 3.16 Operational amplifier (OPAMP) The STM32F303xD/E embed four operational amplifiers with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When an operational amplifier is selected, an external ADC channel is used to enable output measurement. The operational amplifier features: • 8.2 MHz bandwidth • 0.5 mA output capability • Rail-to-rail input/output • In PGA mode, the gain is programmed to be 2, 4, 8 or 16. 3.17 Ultra-fast comparators (COMP) The STM32F303xD/E devices embed seven ultra-fast rail-to-rail comparators with programmable reference voltage (internal or external) and selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output pin • Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 23: Embedded internal reference voltage for the value and precision of the internal reference voltage. All comparators can wake up from STOP mode, generate interrupts and breaks for the timers. 3.18 Timers and watchdogs The STM32F303xD/E include three advanced control timers, up to six general-purpose timers, two basic timers, two watchdog timers and one SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. |
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