STM32F091 datasheet(27/127 Pages) STMICROELECTRONICS

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DocID026284 Rev 3

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STM32F091xB STM32F091xC

Functional overview

3.19

High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the

Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an

environment. It is specified to operate at low speeds with minimum processing and memory

overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC

controller to wakeup the MCU from Stop mode on data reception.

3.20

Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It

can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

3.21

Clock recovery system (CRS)

The STM32F091xB/xC embeds a special block which allows automatic trimming of the

internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device

operational range. This automatic trimming is based on the external synchronization signal,

which could be either derived from LSE oscillator, from an external signal on CRS_SYNC

pin or generated by user software. For faster lock-in during startup it is also possible to

combine automatic trimming with manual trimming action.

3.22

Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected

to the MCU.

STM32F091 数据表(PDF) 27 Page - STMicroelectronics