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STP200N3LL 数据表(PDF) 4 Page - STMicroelectronics |
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STP200N3LL 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 13 page ![]() Electrical characteristics STP200N3LL 4/13 DocID028758 Rev 2 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4: Static Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 30 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 30 V 1 µA VGS = 0 V, VDS = 30 V, Tcase = 125 °C(1) 10 IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 1 2.5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 60 A 2.15 2.4 mΩ VGS = 4.5 V, ID = 60 A 2.5 3.1 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V - 5200 - pF Coss Output capacitance - 640 - Crss Reverse transfer capacitance - 510 - Qg Total gate charge VDD = 15 V, ID = 120 A, VGS = 4.5 V (see Figure 14: "Test circuit for gate charge behavior") - 53 - nC Qgs Gate-source charge - 13 - Qgd Gate-drain charge - 27 - RG Intrinsic gate resistance f = 1 MHz, ID = 0 A, gate DC bias = 0 V, magnitude of alternative signal = 20 mV - 1.1 - Ω Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 15 V, ID = 60 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 18 - ns tr Rise time - 183 - td(off) Turn-off delay time - 90 - tf Fall time - 108 - |
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