VIPER013LSTR datasheet(22/36 Pages) STMICROELECTRONICS

22 / 36 page

General description

VIPer01

22/36

DocID028751 Rev 1

4.11

Overload protection

To manage the overload condition, the IC embeds the following main blocks: the OCP

comparator to turn off the power MOSFET when the drain current reaches its limit (IDLIM) ,

the up and down OCP counter to define the turn-off delay time in case of continuous

overload (tOVL = 50 ms typ.) and the timer to define the restart time after protection tripping

(tRESTART = 1 s typ.).

In case of short-circuit or overload, the control level on the inverting input of the PWM

comparator is greater than the reference level fed into the inverting input of the OCP

comparator. As a result, the cycle-by-cycle turn-off of the power switch is triggered by the

OCP comparator instead of PWM comparator. Every cycle where this condition is met, the

OCP counter is incremented and if the fault condition lasts longer than tOVL (corresponding

to the counter end-of-count), the protection is tripped, the PWM is disabled for tRESTART,

then it resumes switching with soft-start and, if the fault is still present, it is disabled again

after tOVL. The OLP management prevents IC from operating indefinitely at IDLIM and the low

repetition rate of the restart attempts of the converter avoids IC overheating in case of

repeated fault events.

After the fault removal, the IC resumes working normally. If the fault is removed earlier than

the protection tripping (before tOVL), the tOVL-counter is decremented on a cycle-by-cycle

basis down to zero and the protection is not tripped. If the fault is removed during tRESTART,

the IC waits for the tRESTART period has elapsed before resuming switching.

In fault condition the VCC ranges between VCSon and VCCon levels, due to the periodical

activation of the HV current source recharging the VCC capacitor.

Figure 29: Short-circuit condition

4.12

Max. duty cycle counter protection

The IC embeds a max. duty cycle counter, which disables the PWM if the MOSFET is

turned off by max. duty cycle (70% min., 80% max.) for ten consecutive switching cycles.

After protection tripping, the PWM is stopped for tRESTART and then activated again with soft-

start phase until the fault condition is removed.

In some cases (i.e. breaking of the loop) even if VCOMP is saturated high, the OLP cannot be

triggered because at every switching cycle the PWM is turned off by maximum duty cycle

before than DRAIN peak current reaches the IDLIM setpoint. As a result, the output voltage

VOUT can increase without control by keeping a value much higher than the nominal one

with the risk for the output capacitor, the output diode and the IC itself. The max. duty cycle

counter protection avoids this kind of failures.

VIPER013LSTR 数据表(PDF) 22 Page - STMicroelectronics

VIPER013LSTR 数据表(HTML) 22 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载