FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or specifications without notice.

21

Data# Polling TImings (During Embedded Algorithms)

Toggle Bit Timings (During Embedded Algorithms)

Note

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUS

Complement

True

Addresses

VA

tOEH

tCE

tCH

tOH

tDF

VA

VA

Status Data

Complement

Status Data

True

Valid Data

Valid Data

tACC

tRC

Note

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array

data read cycle.

WE#

CE#

OE#

High Z

tOE

DQ6/DQ2

RY/BY#

tBUS

Addresses

VA

tOEH

tCE

tCH

tOH

tDF

VA

VA

tACC

tRC

Valid Data

Valid Status

Valid Status

(first read)

(second read)

(stops toggling)

Valid Status

VA