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MIC5891YN 数据表(PDF) 7 Page - Microchip Technology |
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MIC5891YN 数据表(HTML) 7 Page - Microchip Technology |
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7 / 18 page ![]() 2016 Microchip Technology Inc. DS20005638A-page 7 MIC5891 3.0 TIMING CONDITIONS The descriptions of the timing conditions are listed below Figure 3-1. FIGURE 3-1: Timing Conditions. L = Low Logic Level, H = High Logic Level, X = Irrelevant, P = Present State, R = Previous State. TABLE 3-1: TIMING CONDITIONS PARAMETERS VDD = 5.0V, Logic levels are VDD and ground. Reference Parameter Value A Minimum data active time before clock pulse (data set-up time) 75 ns B Minimum data active time after clock pulse (data hold time) 75 ns C Minimum data pulse width 150 ns D Minimum clock pulse width 150 ns E Minimum time between clock activation and strobe 300 ns F Minimum strobe pulse width 100 ns G Typical time between strobe activation and output transition 1.0 µs H Turn-off delay See Electrical Characteristics I Turn-on delay See Electrical Characteristics CLOCK DATA IN STROBE OUTPUT ENABLE OUTN B D F E C G A H I TABLE 3-2: TRUTH TABLE Serial Data Input Clock Input Shift Register Contents Serial Data Output Strobe Input Latch Contents Output Enable Output Content I1 I2 I3 ... IN-1 IN I1 I2 I3 ... IN-1 IN I1 I2 I3 ... IN-1 IN HH R1 R2 ... RN-2 RN-1 RN-1 —— —— LL R1 R2 ... RN-2 RN-1 RN-1 XR1 R2 R3 ... RN-1 RN RN —— X X X ... X X X L R1 R2 R3 ... RN-1 RN P1 P2 P3 ... PN-1 PN PN HP1 P2 P3 ... PN-1 PN LP1 P2 P3 ... PN-1 PN — — — X X X ... X X H L L L ... L L |
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