MCP79401-ISLASHMS datasheet(35/62 Pages) MICROCHIP

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DS20005009F-page 35

MCP79400/MCP79401/MCP79402

6.0

ON-BOARD MEMORY

The MCP7940X has eight bytes of protected EEPROM

for storing crucial information and 64 bytes of SRAM for

general purpose usage. The SRAM is retained when

the primary power supply is removed if a backup supply

is present and enabled. Since the EEPROM is

nonvolatile, it does not require a supply for data

retention.

Although the SRAM is a separate block from the RTCC

registers, they are accessed using the same control

byte, ‘1101111X’. The EEPROM is in a different

address space and requires the use of a different

control byte, ‘1010111X’.

6.1

SRAM/RTCC Registers

The RTCC registers are located at addresses 0x00 to

0x1F, and the SRAM is located at addresses 0x20 to

0x5F. The SRAM can be accessed while the RTCC

registers are being internally updated. The SRAM is not

initialized by a Power-On Reset (POR).

Neither the RTCC registers nor the SRAM can be

accessed when the device is operating off the backup

power supply.

6.1.1

SRAM/RTCC REGISTER BYTE

WRITE

Following the Start condition from the master, the

control code and the R/W bit (which is a logic low) are

clocked onto the bus by the master transmitter. This

indicates to the addressed slave receiver that the

address byte will follow after it has generated an

Acknowledge bit during the ninth clock cycle.

Therefore, the next byte transmitted by the master is

the address and will be written into the Address Pointer

the

MCP7940X.

After

receiving

another

Acknowledge bit from the MCP7940X, the master

device transmits the data byte to be written into the

addressed memory location. The MCP7940X stores

the data byte into memory and acknowledges again,

and

the

master

generates

Stop

condition

(Figure 6-1).

If an attempt is made to write to an address past 0x5F,

the MCP7940X will not acknowledge the address or

data bytes, and no data will be written. After a byte

Write command, the internal Address Pointer will point

to the address location following the one that was just

written.

6.1.2

SRAM/RTCC REGISTER

SEQUENTIAL WRITE

The write control byte, address, and the first data byte

are transmitted to the MCP7940X in the same way as

in a byte write. But instead of generating a Stop

condition, the master transmits additional data bytes.

Upon receipt of each byte, the MCP7940X responds

with an Acknowledge, during which the data is latched

into memory and the Address Pointer is internally

incremented by one. As with the byte write operation,

the master ends the command by generating a Stop

condition (Figure 6-2).

There is no limit to the number of bytes that can be

written in a single command. However, because the

RTCC registers and SRAM are separate blocks, writing

past the end of each block will cause the Address

Pointer to roll over to the beginning of the same block.

Specifically, the Address Pointer will roll over from 0x1F

to 0x00, and from 0x5F to 0x20.

FIGURE 6-1:

SRAM/RTCC BYTE WRITE

FIGURE 6-2:

SRAM/RTCC SEQUENTIAL WRITE

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

ADDRESS

BYTE

DATA

S 110 1

1 11

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

ADDRESS

BYTE

DATA BYTE 0

DATA BYTE N

S 1 101

111

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