IS1871SF datasheet(13/44 Pages) MICROCHIP

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 2015-2016 Microchip Technology Inc.

DS60001371C-Page 13

IS1870/71

2.0

SYSTEM BLOCK DETAILS

2.1

System Block Descriptions

Each system block of the IS1870/71 is described in this

section.

2.1.1

PMU

The IS1870/71 includes a DC-DC converter and four

LDOs. These LDOs can be configured for various

operating modes and applications to suppress the peak

current and maximize battery life, see Figure 2-1.

FIGURE 2-1:

IS1870/71 POWER TREE

2.1.2

AON

AON is the hardware-based state machine that con-

trols the power-up and power sequence. It includes a

RTC timer and an I/O detector, which can wake-up the

system from Standby mode or Power-Saving mode

using time-out or I/O transition.

2.1.3

The IS1870/71 has an on-chip RF circuit, a controller,

and a modulator (Tx)/demodulator (Rx). The Tx is used

to control the synthesizer's phase and output power,

and modulate the

data based

the BLE

specifications. The Rx is used to decode the Bluetooth

signal and optimize the performance, such as IQ-

imbalance, suppress DC, and flick noise. It is also used

to compensate the frequency drift and offset, filter out

interference to maximize receiver sensitivity.

2.1.4

PERIPHERALS

The IS1870/71 interface is built-in to connect external

MCU and sensors.

2.1.5

MCU

The IS1870/71 has an 8051 core ROM, RAM,

embedded Flash to schedule the BLE tasks, process

BLE protocol stacks, and profiles.

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