Engineering Bulletin

Power Applied Reset

EB413

MOTOROLA

11

Power Applied Reset

It is often a requirement of the application that an external circuit controls

the reset of the MCU. In these conditions, reset may be applied and

released without power down of the application. The 4064-cycle delay is

only applicable to a power-on condition or after the MCU comes out of

stop mode. In each case the oscillator must be restarted and so a short

delay for the oscillator to stabilize is required. When a reset pulse is

subsequently received, the oscillator continues to run and there is no

start-up delay. See Power-On Reset and External Reset Timing for

the MC68HC05J1 for timing diagrams showing power-on reset and the

external reset. The minimum low time for the reset pulse is 1.5 times the

bus cycle time to ensure that a full reset occurs. It is up to the user to

ensure that the minimum low time is met. A shorter low time may cause

a partial reset of the MCU.

Power-On Reset and External Reset Timing for the MC68HC05J1

Figure 3. Power-On Reset Timing

07FE

OSC1 PIN

INTERNAL

CLOCK

INTERNAL

ADDRESS BUS

Notes:

INTERNAL

DATA BUS

07FE

07FE

07FE

07FE

07FE

07FF

(NOTE 1)

1. Power-on reset threshold is typically between 1 V and 2 V.

2. Internal clock, internal address bus, and internal data bus are not available externally.

NEW

PCH

NEW

PCL

Freescale Semiconductor, Inc.

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