LAN9250 datasheet(39/421 Pages) MICROCHIP

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DS00001913A-page 39

LAN9250

6.2.1

CHIP-LEVEL RESETS

A chip-level reset event activates all internal resets, effectively resetting the entire device. A chip-level reset is initiated

by assertion of any of the following input events:

• Power-On Reset (POR)

• RST# Pin Reset

Chip-level reset/configuration completion can be determined by first polling the Byte Order Test Register (BYTE_TEST).

The returned data will be invalid until the Host interface resets are complete. Once the returned data is the correct byte

ordering value, the Host interface resets have completed.

The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configura-

tion Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set. When set, the READY bit

indicates that the reset has completed and the device is ready to be accessed.

With the exception of the Hardware Configuration Register (HW_CFG), Power Management Control Register (PMT_C-

TRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal

resources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READY

bit is set.

A chip-level reset involves tuning of the variable output level pads, latching of configuration straps and generation of the

master reset.

CONFIGURATION STRAPS LATCHING

During POR or RST# pin reset, the latches for the straps are open. Following the release of POR or RST# pin reset, the

latches for the straps are closed.

VARIABLE LEVEL I/O PAD TUNING

Following the release of the POR or RST# pin resets, a 1 uS pulse (active low), is sent into the VO tuning circuit. 2 uS

later, the output pins are enabled. The 2 uS delay allows time for the variable output level pins to tune before enabling

the outputs and also provides input hold time for strap pins that are shared with output pins.

MASTER RESET AND CLOCK GENERATION RESET

Following the enabling of the output pins, the reset is synchronized to the main system clock to become the master

reset. Master reset is used to generate the local resets and to reset the clocks generation.

6.2.1.1

Power-On Reset (POR)

A power-on reset occurs whenever power is initially applied to the device or if the power is removed and reapplied to

the device. This event resets all circuitry within the device. Configuration straps are latched and EEPROM loading is

performed as a result of this reset. The POR is used to trigger the tuning of the Variable Level I/O Pads as well as a

chip-level reset.

Following valid voltage levels, a POR reset typically takes approximately 21 ms, plus any additional time (91 us per byte)

for data loaded from the EEPROM. A full 64KB EEPROM load would complete in approximately 6 seconds.

RST# Pin Driven Low

TABLE 6-1:

RESET SOURCES AND AFFECTED DEVICE FUNCTIONALITY (CONTINUED)

Module/

Functionality

POR

RST#

Digital

Reset

Note

POR is performed by the XTAL voltage regulator, not at the system level

POR is performed internal to the voltage regulators

POR is performed internal to the PHY

Strap inputs are not re-latched, however Soft-straps are returned to their previously latched pin defaults before they

are potentially updated by the EEPROM values.

Part of EEPROM loading

Only those output pins that are used for straps

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