LAN9250 datasheet(104/421 Pages) MICROCHIP

104 / 421 page

LAN9250

DS00001913A-page 104

 2015 Microchip Technology Inc.

For reads, the address is set to access the lower BYTE of the Configuration Register and FIFOSEL is held low. Read

data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. The cycle repeats for the remaining BYTEs

of the Configuration Register, if desired by the host.

9.5.6.2

Index Register Data Access

The figures in this section detail index register read and write operations in indexed address mode for 16 and 8-bit

modes.

16-BIT READ AND WRITE

For writes, the address is set to access the lower WORD of one of the Index Registers and FIFOSEL is held low. Data

on D[15:0] is written on the trailing edge of WR. The cycle repeats for the upper WORD of the Index Register, if desired

by the host.

For reads, the address is set to access the lower WORD of one of the Index Registers and FIFOSEL is held low. Read

data is driven on D[15:0] during RD active. The cycle repeats for the upper WORD of the Index Register, if desired by

the host.

FIGURE 9-26:

INDEXED ADDRESSING CONFIGURATION REGISTER ACCESS - 8-BIT WRITE/

READ

Note:

The upper WORD of Index Registers is reserved and don’t care. Therefore reads and writes to that WORD

are not useful.

CONFIG,2'b00

D[15:8]

A[4:0]

CONFIG,2'b01

Data 7:0

D[7:0]

Data 15:8

FIFOSEL

CONFIG,2'b00

CONFIG,2'b01

CONFIG,2'b10

CONFIG,2'b11

Data 23:16

Data 31:24

Hi-Z

Data 7:0

Data 15:8

Data 23:16

Data 31:24

CONFIG,2'b10

CONFIG,2'b11

LAN9250 数据表(PDF) 104 Page - Microchip Technology

LAN9250 数据表(HTML) 104 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载