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MCP4821 数据表(PDF) 19 Page - Microchip Technology

部件名 MCP4821
功能描述  SPI Interface with 20 MHz Clock Support
PDF  50 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP4821 数据表(HTML) 19 Page - Microchip Technology

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 2010-2015 Microchip Technology Inc.
DS20002249B-page 19
MCP4802/4812/4822
4.1.3
POWER-ON RESET CIRCUIT
The internal Power-on Reset (POR) circuit monitors the
power
supply
voltage
(VDD) during the device
operation. The circuit also ensures that the DAC
powers up with high output impedance (<SHDN> = 0,
typically 500 k
. The devices will continue to have a
high-impedance output until a valid write command is
received and the LDAC pin meets the input low
threshold.
If the power supply voltage is less than the POR
threshold (VPOR = 2.0V, typical), the DACs will be held
in their Reset state. The DACs will remain in that state
until VDD > VPOR and a subsequent write command is
received.
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the VDD pin, can
provide additional transient immunity.
FIGURE 4-3:
Typical Transient Response.
4.1.4
SHUTDOWN MODE
The user can shut down each DAC channel selectively
using a software command (<SHDN> = 0). During
Shutdown mode, most of the internal circuits in the
channel that was shut down are turned off for power
savings. The internal reference is not affected by the
shutdown command. The serial interface also remains
active, thus allowing a write command to bring the
device out of the Shutdown mode. There will be no
analog output at the channel that was shut down and
the VOUT pin is internally switched to a known resistive
load (500 k
 typical. Figure 4-4 shows the analog
output stage during the Shutdown mode.
The device will remain in Shutdown mode until the
<SHDN> bit = 1 is latched into the device. When a
DAC channel is changed from Shutdown to Active
mode, the output settling time takes < 10 µs, but
greater than the standard active mode settling time
(4.5 µs).
FIGURE 4-4:
Output Stage for Shutdown
Mode.
Transients above the curve
will cause a reset
Transients below the curve
will NOT cause a reset
5V
Time
Transient Duration
VPOR
VDD - VPOR
TA = +25°C
10
8
6
4
2
0
12
3
4
5
VDD - VPOR (V)
500 k
Power-Down
Control Circuit
Resistive
Load
VOUT
Op
Amp
Resistive String DAC



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