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APDS-9500 数据表(PDF) 2 Page - AVAGO TECHNOLOGIES LIMITED |
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APDS-9500 数据表(HTML) 2 Page - AVAGO TECHNOLOGIES LIMITED |
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2 / 36 page ![]() 2 I/O Pins Configuration Pin Name Type Description 1 NC No connect 2 INT O Interrupt 3 GND Power supply ground 4 SPI_DATA O SPI data 5 SPI_CLK O SPI clock 6 NC No connect 7 LDR_2 LED Drive 2 8 LED-K_1 LED Cathode 9 LED-A LED anode, connect to VLED on PCB 10 VDDA_I/O Connect to GND through decoupling capacitor 11 VDDAY_I/O Connect to GND through decoupling capacitor 12 VDDA18_I/O Connect to GND through decoupling capacitor 13 VDD Power supply voltage 14 VIO Power supply voltage 15 SPI_MCLK I SPI master clock 16 SPI_CSn O SPI chip select 17 I2C_SDA I/O I2C-bus serial data I/O terminal—serial data I/O for I2C-bus 18 I2C_SCL I I2C-bus serial clock input terminal—clock signal for I2C-bus serial data Functional Block Diagram Sensor Array 9-bit A/D SPI Master Timing Gen. Reg. Bank I2C Power Block I2C_SDA I2C_SCL VDD GND SPI_MCLK SPI_CSn SPI_CLK SPI_DATA Frame Buffer (Frame subtraction) 30x30 LED Driver 60x60 Pre Processing VIO Object Extraction Gesture Recognition Interrupt INT IR LED |
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