IDT7005S datasheet(8/21 Pages) IDT

部件名	IDT7005S

功能描述	HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

PDF	21 Pages

Scroll/Zoom	100%

制造商	IDT [Integrated Device Technology]

网页	http://www.idt.com

标志

8 / 21 page

6.42

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

tRC

ADDR

tAA

(4)

2738 drw 07

tACE

(4)

tAOE

(4)

tLZ

(1)

tOH

tHZ

(2)

tBDD

(3,4)

DATAOUT

BUSYOUT

VALID DATA

(4)

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

2738 drw 08

tPU

ICC

ISB

tPD

IDT7005S 数据表(PDF) 8 Page - Integrated Device Technology

IDT7005S 数据表(HTML) 8 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

数据表下载