MEGAWIN

MLC0xxB Series Technical Summary

13

DIV1 interrupt selector (If the frequency of divider 1 clock source is 32.768KHz)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

00CEH

DIV1_STL

128

Hz

256

Hz

512

Hz

1024

Hz

2048

Hz

4096

Hz

8192

Hz

16384

Hz

√

-

00CFH

DIV1_STH

0.5Hz

1Hz

2Hz

4Hz

8Hz

16Hz

32Hz

64Hz

√

-

00CEH

DIV1x_SEL

CKI7

CKI6

CKI5

CKI4

CKO3

CKO2

CKO1

CKO0

-

√

The divider 1 contents can be reset to 00H by POR, reset, waken from STOP mode and writing

DIV1x_SEL register any value.

CKI6

CKI5

CKI4

Selected DIV1 input frequency

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

CKO3

CKO2

CKO1

CKO0

Selected DIV1x frequency

0

0

0

0

(16384 Hz)

0

0

0

1

(8192 Hz)

0

0

1

0

(4096 Hz)

0

0

1

1

(2048 Hz)

0

1

0

0

(1024 Hz)

0

1

0

1

(512 Hz)

0

1

1

0

(256 Hz)

0

1

1

1

(128 Hz)

1

0

0

0

(64 Hz)

1

0

0

1

(32 Hz)

1

0

1

0

(16 Hz)

1

0

1

1

(8 Hz)

1

1

0

0

(4 Hz)

1

1

0

1

(2 Hz)

1

1

1

0

(1 Hz)

1

1

1

1