HT46R22 datasheet(21/46 Pages) HOLTEK

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HT46R22/HT46C22

Rev. 1.10

October 2, 2002

3: Set EHI bit of the interrupt control register 1 (INTC1)

bit 0 to enable the I

2C BUS interrupt.

Label

(HSR)

Bits

Function

HCF

HCF is clear to

²0² when one data byte is

being transferred, HCF is set to

²1² indi-

cating 8-bit data communication has

been finished.

HAAS

HAAS is set to

²1² when the calling ad-

dressed is matched, and I

2C BUS inter-

rupt will occur and HIF is set.

HBB

HBB is set to

²1² when I2C BUS is busy

and HBB is cleared to

²0² means that

the I

2C BUS is not busy.

Unused bit, read as

²0²

Unused bit, read as

²0²

SRW

SRW is set to

²1² when the master

wants to read data from the I

2C BUS, so

the slave must transmit data to the mas-

ter. SRW is cleared to

²0² when the

master wants to write data to the I

BUS, so the slave must receive data

from the master.

Unused bit, read as

²0²

RXAK

RXAK is cleared to

²0² when the master

receives an 8-bit data and acknowledg-

ment at the 9th clock, RXAK is set to

²1²

means not acknowledged.

HSR register

Start signal

The START signal is generated only by the master de-

vice. The other device in the bus must detect the START

signal to set the I

2C BUS busy bit (HBB). The START

signal is SDA line from high to low, when SCL is high.

Slave address

The master must select a device for transferring the

data by sending the slave device address after the

START signal. All device in the I

2C BUS will receive the

2C BUS slave address (7 bits) to compare with its own

slave address (7 bits). If the slave address is matched,

the slave device will generate an interrupt and save the

following bit (8th bit) to SRW bit and sends an acknowl-

edge bit (low level) to the 9th bit. The slave device also

sets the status flag (HAAS), when the slave address is

matched.

In interrupt subroutine, check HAAS bit to know whether

the I

2C BUS interrupt comes from a slave address that is

matched or a data byte transfer is completed. When the

slave address is matched, the device must be in trans-

mit mode or receive mode and write data to HDR or

dummy read from HDR to release the SCL line.

S C L

S t a r t

S D A

S R W

A C K

D a t a

A C K

S t o p

S = S t a r t ( 1 b i t )

S A = S l a v e A d d r e s s ( 7 b i t s )

S R = S R W

b i t ( 1 b i t )

M = S l a v e d e v i c e s e n d a c k n o w l e d g e b i t ( 1 b i t )

D = D a t a ( 8 b i t s )

A = A C K ( R X A K b i t f o r t r a n s m i t t e r ; T X A K b i t f o r r e c e i v e r 1 b i t )

P = S t o p ( 1 b i t )

S A

S R

S A

S R

S C L

S D A

Slave address

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