HT46R23 datasheet(21/42 Pages) HOLTEK

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HT46R23

Rev. 1.30

August 17, 2001

3: Set EHI bit of the interrupt control register 1 (INTC1)

bit 0 to enable the I2C BUS interrupt.

Label

(HSR) Bits

Function

HCF

HCF is clear to ²0² when one data byte is

being transferred, HCF is set to ²1² indi-

cating 8-bit data communication has

been finished.

HAAS

HAAS is set to ²1² when the calling ad-

dressed is matched, and I2C BUS inter-

rupt will occur and HIF is set.

HBB

HBB is set to ²1² when I2C BUS is busy

and HBB is cleared to ²0² means that

the I2C BUS is not busy.

4 Unused bit, read as ²0²

3 Unused bit, read as ²0²

SRW

SRW is set to ²1² when the master

wants to read data from the I2C BUS, so

the slave must transmit data to the mas-

ter. SRW is cleared to ²0² when the

master wants to write data to the I2C

BUS, so the slave must receive data

from the master.

1 Unused bit, read as ²0²

RXAK

RXAK is cleared to ²0² when the master

receives an 8-bit data and acknowledg-

ment at the 9th clock, RXAK is set to ²1²

means not acknowledged.

HSR register

Start signal

The START signal is generated only by the master de-

vice. The other device in the bus must detect the START

signal to set the I2C BUS busy bit (HBB). The START

signal is SDA line from high to low, when SCL is high.

Slave address

The master must select a device for transferring the

data by sending the slave device address after the

START signal. All device in the I2C BUS will receive the

I2C BUS slave address (7 bits) to compare with its own

slave address (7 bits). If the slave address is matched,

the slave device will generate an interrupt and save the

following bit (8th bit) to SRW bit and sends an acknowl-

edge bit (low level) to the 9th bit. The slave device also

sets the status flag (HAAS), when the slave address is

matched.

In interrupt subroutine, check HAAS bit to know whether

the I2C BUS interrupt comes from a slave address that is

matched or a data byte transfer is completed. When the

slave address is matched, the device must be in trans-

mit mode or receive mode and write data to HDR or

dummy read from HDR to release the SCL line.

SRW bit

The SRW bit means that the master device wants to

read from or write to the I2C BUS. The slave device

check this bit to understand itself if it is a transmitter or a

receiver. The SRW bit is set to ²1² means that the mas-

ter wants to read data from the I2C BUS, so the slave de-

Da t a

AC K

St o p

S = S t ar t ( 1 bi t )

S A = S l a ve A d d r e ss ( 7 b i t s)

S R = S R W

b i t ( 1 b i t)

M = S l av e dev i ce s e nd a cl cnow l edge bi t ( 1 b i t )

D = D a ta ( 8 b i ts )

A = A C K ( R X A K b i t fo r tr a n s m i tte r ; T X A K b i t fo r r e ce i v e r 1 b i t)

P = S t op ( 1bi t )

SC L

St a r t

SD A

SR W

A C K

01010

SC L

SD A

Slave address

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