71342LA55JG8 datasheet(7/14 Pages) IDT

7 / 14 page

6.42

IDT71342SA/LA

High-Speed 4K x 8 Dual-Port Static RAM with Semaphore

Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)

NOTES:

1. Write cycle parameters should be adhered to, in order to ensure proper writing.

2. CEL = CER = VIL. CE"B" = VIL.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

Timing Waveform of Read Cycle No. 2, Either Side(1,3)

Timing Waveform of Write with Port-to-Port Read(2,3)

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = VIH and OE = VIL, unless otherwise noted.

4. Start of valid data depends on which timing becomes effective last; tAOE, tACE, or tAA

5. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for SRAM Address Access and tSAA is for Semaphore Address Access.

tAA or tSAA

ADDRESS

DATAOUT

PREVIOUS DATA VALID

DATA VALID

tOH

tRC

2721 drw 07

2721 drw 08

CE or SEM

DATAOUT

VALID DATA

tPD

tAOE

tACE

tHZ

tLZ

tPU

50%

ICC

ISB

CURRENT

tHZ

tSOP

(5)

tSOP

(1)

(4)

(2)

(4)

2721 drw 09

W "A"

VALID

tWC

MATCH

VALID

MATCH

tWP

tDW

tWDD

tDDD

ADDR "A"

DATAIN "A"

DATAOUT "B"

ADDR "B"

(1)

tDH

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