ICS663

MDS 663 D

1

Revision 062904

Description

The ICS663 is a low cost Phase-Locked Loop (PLL)

designed for clock synthesis and synchronization.

Included on the chip are the phase detector, charge

pump, Voltage Controlled Oscillator (VCO) and an

output buffer. Through the use of external reference

and VCO dividers (implemented with the ICS674-01,

for example), the user can easily configure the device

to lock to a wide variety of input frequencies.

The phase detector and VCO functions of the device

can also be used independently. This enables the

configuration of other PLL circuits. For example, the

ICS663 phase detector can be used to control a VCXO

circuit such as the MK3754.

For applications requiring Power Down or Output

Enable features, please refer to the ICS673-01.

Features

to 120 MHz (5 V)

wide range of input frequencies

(video Hsync, for example)

PLL circuit

independently for other PLL configurations

Block Diagram

REF IN

P hase/

Frequency

De te cto r

VCO

4

2

SEL

LFR

LF

UP

FBIN

DOW N

I

cp

I

cp

CL K

VDD

MU X

1

0

E xternal F eedback D ivider

(such as the IC S 674-01)

C lock Input