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ICS950202 数据表(PDF) 10 Page - Integrated Circuit Systems |
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ICS950202 数据表(HTML) 10 Page - Integrated Circuit Systems |
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10 / 19 page ![]() 10 Integrated Circuit Systems, Inc. ICS950202 0461L—05/28/03 Byte 17: Output Divider Control Register Byte 18: Group Skew Control Register Byte 19: Group Skew Control Register Table 1 Table 2 ) 2 : 3 ( v i D 0 01 00 11 1 ) 0 : 1 ( v i D 0 02 /4 /8 /6 1 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 17 /4 1 /8 2 /6 5 / ) 2 : 3 ( v i D 0 01 00 11 1 ) 0 : 1 ( v i D 0 04 /8 /6 1 /2 3 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 19 /8 1 /6 3 /2 7 / t i Be m a ND W Pn o i t p i r c s e D 7 t i B1 w e k S _ U P C0 o t t c e p s e r h t i w 2 T / C K L C U P C e h t y a l e d s t i b 2 e s e h T ) 0 : 1 ( T / C K L C U P C s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 s p 0 5 2 = 1 0 s p 0 = 0 0 6 t i B0 w e k S _ U P C0 5 t i Bd e v r e s e R0 d e v r e s e R 4 t i Bd e v r e s e R0 d e v r e s e R 3 t i B1 w e k S _ U P C0 e h t y a l e d s t i b 2 e s e h T) 0 : 1 ( T / C K L C U P Co t t c e p s e r h t i w k c o l c 2 T / C K L C U P C s p 0 5 2 = 1 0 s p 0 = 0 0s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 2 t i B0 w e k S _ U P C0 1 t i Bd e v r e s e R0 d e v r e s e R 0 t i Bd e v r e s e R0 d e v r e s e R t i Be m a ND W Pn o i t p i r c s e D 7 t i BV N I _ 6 6 V 30 t i b n o i s r e v n I e s a h P 0 _ 6 6 V 3 6 t i BV N I _ 6 6 V 30 t i b n o i s r e v n I e s a h P ) 1 : 3 ( 6 6 V 3 5 t i BV N I _ U P C0 t i b n o i s r e v n I e s a h P 2 U P C 4 t i BV N I _ U P C0 t i b n o i s r e v n I e s a h P ) 0 : 1 ( U P C 3 t i B 3 v i D I C P1 s t i b 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c I C P . 2 e l b a T o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o F . y ll a u d i v i d n i . r e d i v i d S F d e h c t a l s i p u r e w o p t a t l u a f e D 2 t i B 2 v i D I C P0 1 t i B 1 v i D I C P0 0 t i B 0 v i D I C P1 Bit Name PWD Description Bit 7 3V66_Skew 1 1 These 2 bits delay the 3V66 (3:2) with respect to CPUCLK 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Bit 6 3V66_Skew 0 0 Bit 5 Reserved 0 Reserved Bit 4 Reserved 0 Reserved Bit 3 3V66_Skew 1 0 These 2 bits delay the 3V66 (1:0) with respect to CPUCLK 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Bit 2 3V66_Skew 0 1 Bit 1 Reserved 0 Reserved Bit 0 Reserved 0 Reserved |
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