Bit

Description

Comment

11

Right

Playback

PCM Data

1 = Right PCM Data is

valid.

SDATA_OUT Slot 1: Control Address

Slot 1 is used both to write to the LM4546 registers as well

as read back a register’s current value. The MSB of Slot 1

(bit 19) signifies whether the current control operation is a

read or a write. Bits 18 through 12 are used to specify the

register address of the read or write operation. The least sig-

nificant twelve bits are reserved and should be stuffed with

zeros by the AC’97 controller.

Bits

Description

Comment

19

Read/Write

0 = Read, 1 = Write

18:12

Control

Register

Identifies the Control

Register

11:0

Reserved

Set to

″0″

SDATA_OUT Slot 2: Control Data

Slot 2 is used to transmit 16 bit control data to the LM4546 in

the event that the current operation is a write operation. The

least significant four bits should be stuffed with zeros by the

AC ’97 controller. If the current operation is a register read,

the entire slot, bits 19 through 0 should be stuffed with zeros.

Bits

Description

Comment

19:4

Control

Register Write

Data

Set bits to

″0″ if read

operation

3:0

Reserved

Set to

″0″

SDATA_OUT Slot 3: PCM Playback Left Channel

Slot 3 is a 20 bit field used to transmit data intended for the

left DAC on the LM4546. Any unused bits should be padded

with zeros. The LM4546 DACs have 18 bit resolution and

thus will use the first 18 bits of the 20 bit PCM stream.

Bits

Description

Comment

19:0

PCM Audio

Data for Left

DAC

Set unused bits to

″0″

SDATA_OUT Slot 4: PCM Playback Right Channel

Slot 4 is a 20 bit field used to transmit data intended for the

right DAC on the LM4546. Any unused bits should be pad-

ded with zeros. The LM4546 DACs have 18 bit resolution

and thus will use the first 18 bits of the 20 bit PCM stream.

Bits

Description

Comment

19:0

PCM Audio

Data for Right

DAC

Set unused bits to

″0″

SDATA_OUT Slots 5-12: Reserved

Set these SDATA_OUT slots to

″0″ as they are not currently

implemented and are reserved for future use.

AC Link Input Frame: SDATA_IN (input to controller,

output from LM4546)

The audio input frame (input to the AC ’97 Digital Controller)

contains status and PCM data from the LM4546 control reg-

isters and stereo ADC. The Tag slot, slot 0, contains 16 bits

that tell the AC ’97 Digital Controller whether the LM4546 is

ready and the validity of data from certain device subsec-

tions.

A new audio input frame is signaled with a low to high tran-

sition of SYNC. SYNC is synchronous to the rising edge of

BIT_CLK. On the next rising edge of BIT_CLK, the LM4546

drives SDATA_IN with the first bit of slot 0. The Digital Con-

troller samples SDATA_IN on the falling edge of BIT_CLK.

The LM4546 will continue outputting the SDATA_IN stream

on each successive rising edge of BIT_CLK. The LM4546

outputs data MSB first, in a MSB justified format. All reserved

bits and slots are stuffed with

″0″ ’s by the LM4546.

SDATA_IN Slot 0: Codec Status Bits

The first bit of SDATA_IN Slot 0 (bit 15) indicates when the

Codec is ready. The digital controller must probe further to

see which other subsections are ready.

DS100985-8

FIGURE 6. AC Link Audio Input Frame

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