CPC5903

R02

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9

dependent on the end product’s design criteria and the

operational characteristics of the CPC5903.

On Side A of the CPC5903, pull-ups chosen for

Fast-mode (up to 6mA) drivers can be used with no

loss of noise margin.

At the Side B outputs, OB and IOB, pull-up resistor

values should be chosen for Standard-mode 3mA

on IOB must be large enough that the weakest driver

on the Side B bus can pull the voltage reliably below

outputs will drive up to 6mA, and resistor pull-ups

chosen for up to 6mA can be used, provided all the

other devices on the bus have sufficient drive.

3.5 Pulse Propagation, Stretching and Delays

Due to glitch protection circuitry within the CPC5903

applying a pulse at the IOB input inherently involves

the use of the output driver at that I/O. Once an

asserted signal at IOB is determined to be valid, it is

stretched until it’s transmission through the optics has

been verified. This insures that there will be no extra

edges generated at either side due to optic delays. If a

Side B asserted-low pulse is long enough to be

accepted and passed to Side A, then the flip-flop at

Side B is set and remains set until the signal returns

through the optics from Side A. While the flip-flop is

set, IOB will output a voltage limited logic low, thereby

holding the bus at a logic low.

In operation, a valid asserted pulse of less than 80ns

applied at IOB appears at Side A after a delay largely

Side A driver IOA is activated and a logic low is

asserted at time:

That assertion is returned across the optics to Side B

arriving at Side B, the flip-flop is cleared with the

incoming signal from Side A sustaining the IOB

voltage limited logic low. With the prior loss of the

because the IOB input does not accept it’s own output

low as valid, a deassertion is sent through the optics to

Side A, arriving at the Side A output after a delay

Thus a valid Side B pulse having a width less than

80ns is stretched at Side A to a typical width of 125ns.

The duration of the pulse width output onto the Side A

bus is given by:

When Side A is deasserted, the output rises at a slew

rate determined by the RC load on IOA, and passes

(logic HIGH) input propagates through the optics and

deasserts the Side B output after a delay largely

Consequently at Side B input, an applied pulse of less

than 80ns is stretched to:

which is typically 330ns. More importantly, only one

pulse is seen at both ports, with no extra or missing

clock or data edges, assuring bus integrity.

Pulses of width larger than approximately 80ns

applied to the Side B input do not utilize the flip-flop to

terminate the pulse, but do need to propagate to

Side A and then back to Side B when returning high

after being asserted low. The Side A pulse width is

given by the usual pulse width distortion relation:

provided in the table, “Electrical Specifications” on

page 4. The pulse at Side B is asserted by an

the end of the pulse, the rising edge passes through

threshold causing the Side A LED drive to deactivate,

which propagates the deasserted state back to Side B